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MP8719 26v, 12a, low i q , high-current, synchronous buck converter with 1a ldo and buffered reference MP8719 rev1.01 www.monolithicpower.com 1 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. the future of analog ic technology description the MP8719 provides a complete power supply with the highest power density for ddr3, ddr3l, lpddr3, and ddr4 memory. the MP8719 integrates a high-frequency, synchronous, rectified, step-down, switch-mode converter (vddq) with a 1a sink/source ldo (vtt) and buffered low-noise reference (vttref). the MP8719 operates at high efficiency over a wide output current load range based on mps?s proprietary switching loss reduction technology and internal low r ds(on) power mosfets. adaptive constant-on-time (cot) control mode provides fast transient response and eases loop stabilization. the dc auto-tune loop provides good load and line regulation. the vtt ldo provides 1a of sink/source current capability and requires only a 22 f ceramic capacitor. the vttref tracks vddq/2 with excellent 1% accuracy. full protection features include over-current (oc) limit, over-voltage protection (ovp), under-voltage protection (uvp), over- temperature warning (otw), and thermal shutdown. the MP8719 requires a minimal number of external components and is available in a qfn- 16 (3mmx3mm) package. features ? wide 4.5v to 26v operating input range ? 135 a low quiescent current ? 12a continous output current ? 13a peak output current ? selectable ultrasonic mode (usm) ? selectable 500khz/700khz switching frequency ? built-in 1a vttldo ? 1% buffered vttref output ? adaptive cot for fast transient ? dc auto-tune loop ? stable with poscap and ceramic output capacitors ? over-temperature warning (otw) ? internal soft start (ss) ? output discharge ? ocl, ovp, uvp, and thermal shutdown ? latch-off reset via en or power cycle ? available in a qfn-16 (3mmx3mm) package applications ? televisions ? networking systems ? distributed power systems ? set-top-box a ll mps parts are lead-free, halogen-free, and adhere to the rohs directive. for mps green status , please visit the mps website unde r quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo MP8719 rev1.01 www.monolithicpower.com 2 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. ordering information part number* package top marking MP8719gq qfn-16 (3mmx3mm) see below * for tape & reel, add suffix ?z (e.g. MP8719gq?z) top marking azf: product code of MP8719gq y: year code lll: lot number package reference top view qfn-16 (3mmx3mm)
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo MP8719 rev1.01 www.monolithicpower.com 3 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. absolute maxi mum ratings (1) supply voltage (vin) .................................... 26v v sw (dc) ................................. -1v to vin + 0.3v v sw (25ns) ............................... -3.6v to vin + 4v v bst ................................................... v sw + 4.5v i en1 , i en2 .................................................... 100a all other pins ................................ -0.3v to +4.5v continuous power dissipation (t a = +25c) (2) qfn-16 (3mmx3mm) ................................. 2.3w junction temperature ................................ 150c lead temperature ..................................... 260c storage temperature ................ -65c to +150c recommended operating conditions (3) supply voltage (vin) ........................ 4.5v to 24v supply voltage (v cc ) ..................... 3.15v to 3.5v output voltage (v ddq ) ................. 0.6v to 3.3v (4) i en1 , i en2 ...................................................... 50 a operating junction temp. (t j ) ... -40c to +125c thermal resistance (5) ja jc qfn-16 (3mmx3mm) ............. 55 ....... 13 ... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max)=(t j (max)- t a )/ ja . exceeding the maximum allowable power dissipation produces an excessive die temper ature, causing the regulato r to go into thermal shutdown. internal thermal shutdown circuitry protects the dev ice from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) for applications that need 3.3v < vout < 5.5v, special design requirements are needed. please refer to the application information section on page 16. vddq must be 3.3v. 5) measured on jesd51-7, 4-layer pcb.
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo MP8719 rev1.01 www.monolithicpower.com 4 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. electrical characteristics vin = 12v, 3v3 = 3.3v, t j = 25c, r mode = 0 ? , unless otherwise noted. parameters symbol condition min typ max units supply current 3v3 supply current in normal mode i 3v3 v en1 = v en2 = 3v, no load 185 a 3v3 supply current in s3 mode i 3v3_s3 v en1 = 0v, v en2 = 3v, no load 135 a 3v3 shutdown current i 3v3 sdn v en1 = v en2 = 0v, no load 1 a mosfet high-side switch on resistance hs rds-on t j = 25c 19.5 m ? low-side switch on resistance ls rds-on t j = 25c 6.6 m ? switch leakage sw lkg v en = 0v, v sw = 0v 0 1 a current limit low-side valley current limit i limit 12 13 14 a switching frequency and minimum off time switching frequency f s r mode = 0 ? 700 khz r mode = 150k ? 500 khz constant on timer t on vin = 6v, v out = 3v, r mode = 150k ? 1100 1200 1300 ns minimum on time ( 6 ) t on min 70 ns minimum off time ( 6 ) t off min 300 ns ultrasonic mode (usm) ultrasonic mode operation period t usm v fb = 0.62v 32 s protection ovp threshold v ovp 125 130 135 %v ref uvp-1 threshold v uvp-1 70% 75% 80% v ref uvp-1 foldback timer ( 6 ) t uvp-1 30 s uvp-2 threshold v uvp-2 45% 50% 55% v ref reference and soft start, soft stop reference voltage v ref 594 600 606 mv feedback current i fb v fb = 0.62v 10 50 na soft-start time t sstart en to pg up 1.8 2.2 2.6 ms soft-stop time t ssto p 2 ms enable (en) and under-voltage lockout (uvlo) en1 rising threshold v en1 th 0.54 0.59 0.64 v en1 hysteresis v en1-hys 125 mv en2 rising threshold v en2 th 1.12 1.22 1.32 v en2 hysteresis v en2-hys 125 mv enable input current i en1/2 v en1/2 = 2v 5 a v en1/2 = 0v 1
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo MP8719 rev1.01 www.monolithicpower.com 5 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. electrical characteristics (continued) vin = 12v, 3v3 = 3.3v, t j = 25c, r mode = 0 ? , unless otherwise noted. parameters symbol condition min typ max units vcc uvlo threshold rising vcc vth 2.9 3.0 3.1 v vcc uvlo threshold hysteresis vcc hys 220 mv vin uvlo threshold rising vin vth 4.2 4.4 v vin uvlo threshold hysteresis vin hys 360 mv power good (pg) pg when fb rising (good) pg risin g( good ) v fb rising, percentage of v fb 95 % pg when fb falling (fault) pg fallin g( fault ) v fb falling, percentage of v fb 90 pg when fb rising (fault) pg risin g( fault ) v fb rising, percentage of v fb 115 pg when fb falling (good) pg fallin g( good ) v fb falling, percentage of v fb 105 pg low to high delay pg td 3 s en low to pg low delay pg td en low 1 s pg sink current capability v pg sink 4ma 0.4 v vttref output vttref output voltage v ttref v ddq /2 output voltage tolerance to vddq v ttref / v ddq i vttref < 0.1ma, 1v < v ddq < 1.5v 49.2% 50% 50.8% i vttref < 10ma, 1v < v ddq < 1.5v 49% 50% 51% current limit i limit vttref 13 15 ma vtt ldo vtt output voltage v tt v ddq /2 vtt tolerance to vttref v tt -v ttref -10ma < i vtt < 10ma, v ddq = [1v - 1.5v] -15 15 mv -0.6a < i vtt < 0.6a, v ddq = [1v - 1.5v] -20 20 mv -1a < i vtt < 1a, v ddq = [1v - 1.5v] -25 25 mv source current limit i limit source 1.2 1.5 a sink current limit i limit sink 1.2 1.5 a otw over-temperature warning ( 6 ) t otw 130 c otw hysteresis ( 6 ) t otw hys 25 c otw sink current capability v otw sink 4ma 0.4 v otw leakage current i otw v otw = 3.3v 1 a otw assertion time ( 6 ) t otw 32 ms thermal protection thermal shutdown ( 6 ) t sd 145 c thermal shutdown hysteresis t sd_hys 25 c note: 6) guaranteed by design.
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo MP8719 rev1.01 www.monolithicpower.com 6 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. pin functions pin # name description 1 vin supply voltage. vin supplies power for the internal mosfet and regulators. the MP8719 operates from a +4.5v to +26v input rail. an input capacitor is needed to decouple the input rail. use wide pcb traces and multiple vias to make the connection. 2 pgnd power ground. use wide pcb traces and multiple vias to make the connection. 3 3v3 external 3v3 vcc input for control and driver. place a 1f decoupling capacitor close to 3v3 and agnd. it is recommended to form an r-c filter. 4 agnd analog ground. the internal reference is referr ed to agnd. connect gnd of the fb divider resistor to agnd for better load regulation. 5 vtt vtt ldo output. decouple with a minimum 22f ceramic capacitor as close to vtt as possible. x7r or x5r grade dielectric ceramic capacitors are recommended for their stable temperatur e characteristics. 6 vddq input of vttldo. vddq is also used for v out sense. do not float vddq at any time. connect vddq to the output capacitor of t he regulator directly with a thick (>100mil) trace. 7 vttref buffered vtt reference output. decouple vttref with a minimum 0.22f ceramic capacitor as close to it as possible. x7r or x5r grade dielectric ceramic capacitors are recommended for their stable temperature characteristics. 8 vtts vtt output sense. connect vtts to the output capaci tor of the vtt regulator directly. 9 sw switch output. connect sw to the inductor and bootstrap capacitor. sw is connected to vin when the hs-fet is on. sw is conne cted to pgnd when the ls-fet is on. use wide and short pcb traces to make the conn ection. sw is noisy, so keep sensitive traces away from sw. 10 bst bootstrap. a capacitor connected between sw and bst is required to form a floating supply across the high-side switch driver. 11 otw over-temperature status. otw is used to indicate that the MP8719 is close to otp. otw is pulled low once the junction temper ature is higher than the over-temperature warning threshold. otw can be left open if not used. 12 pg power good output. pg is an open-drain signal. pg is high if the output voltage is within a proper range. 13 fb feedback. an external resistor divider from t he output to gnd (tapped to fb) sets the output voltage. place the resistor divider as close to fb as possible. avoid vias on the fb traces. 14 mode switching frequency and ultrasonic mode selection. a 1% pull-down resistor is needed on mode. 15 en2 enable. en1 and en2 are digital inputs which are used to enable or disable the internal regulators. once en1 = en2 = 1, the vddq regulator, vtt ldo, and vttref output are turned on. when en1 = 0 and en2 = 1, all the regulator s are on except vtt ldo. all regulators are turned off when en2 = 0 or en1 = en2 = 0. do not float en1 at any time. if the vtt ldo function is not used, tie en1 to gnd. 16 en1
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo MP8719 rev1.01 www.monolithicpower.com 7 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics vin = 20v, vddq = 1.35v, l = 0.68h/3.1m ? , f sw = 700khz, unless otherwise noted.
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo MP8719 rev1.01 www.monolithicpower.com 8 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics (continued) vin = 20v, vddq = 1.35v, l = 0.68h/3.1m ? , f sw = 700khz, unless otherwise noted. v ddq /ac 20mv/div. v sw 20v/div. i l 2a/div. v ddq /ac 20mv/div. v ddq 1v/div. v en2 2v/div. v sw 20v/div. i l 10a/div. v pg 2v/div. i l 2a/div. v ddq 1v/div. v en2 2v/div. v pg 2v/div. i l 5a/div. v ddq 1v/div. v tt 500mv/div. v ttref 500mv/div. v ddq 1v/div. v en2 2v/div. v en2 5v/div. v ddq 1v/div. v tt 500mv/div. v ttref 500mv/div. v en2 5v/div. v ddq 1v/div. v tt 500mv/div. v ttref 500mv/div. v en2 5v/div. v pg 2v/div. i l 10a/div. v ddq 1v/div. v en2 2v/div. v pg 2v/div.
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo MP8719 rev1.01 www.monolithicpower.com 9 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical performanc e characteristics (continued) vin = 20v, vddq = 1.35v, l = 0.68h/3.1m ? , f sw = 700khz, unless otherwise noted. v ddq /ac 50mv/div. v ddq 1v/div. v tt 500mv/div. v vref 500mv/div. v en1 2v/div. v ddq 1v/div. v tt 500mv/div. v vref 500mv/div. v en1 2v/div. v ddq 1v/div. v tt 500mv/div. v vref 500mv/div. v en1 2v/div. v ddq 1v/div. v tt 500mv/div. v vref 500mv/div. v en2 5v/div. v ddq 1v/div. v tt 500mv/div. v vref 500mv/div. v en1 2v/div. v ddq 1v/div. v sw 20v/div. i l 10a/div. v sw 20v/div. i l 5a/div. v ddq 1v/div. v sw 20v/div. i l 10a/div. v ddq 1v/div. v sw 20v/div. i l 10a/div.
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo MP8719 rev1.01 www.monolithicpower.com 10 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. block diagram vtt vddq control vtts vttref en1/en2 control logic on time one shot fault logic soft start por & reference 130% vref ovp oc limit pok min off time fb 95% vref vddq sw bstreg vin bst sw pgnd pg 3v3 output discharge v in dc error correction + + fb ref vref fb en1 agnd en2 otw mode 3v3 uvp-2 uvp-1 75% vref 50% vref figure 1: functional block diagram
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo preliminary specifications subject to change MP8719 rev. 1.01 www.monolithicpower.com 11 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. operation pulse-width modulation (pwm) operation the MP8719 is a fully integrated, synchronous, rectified, step-down, switch-mode converter with 1a of ldo current. constant-on-time (cot) control provides fast transient response and eases loop stabilization. at the beginning of each cycle, the high-side mosfet (hs-fet) is turned on when the feedback voltage (v fb ) is below the reference voltage (v ref ), which indicates an insufficient output voltage. the on period is determined by both the output voltage and the input voltage to make the switching frequency fairly constant over the input voltage range. after the on period elapses, the hs-fet is turned off or enters an off state. the hs-fet is turned on again when v fb drops below v ref . by repeating operation this way, the converter regulates the output voltage. the integrated low-side mosfet (ls-fet) is turned on when the hs-fet is in its off state to minimize conduction loss. a dead short occurs between the input and gnd if both the hs-fet and the ls-fet are turned on at the same time. this is called shoot-through. to prevent shoot-through, a dead time (dt) is generated internally between the hs-fet off and the ls-fet on period or the ls-fet off and the hs-fet on period. internal compensation is applied for cot control for stable operation, even when ceramic capacitors are used as output capacitors. this internal compensation improves jitter performance without affecting the line or load regulation. heavy-load operation continuous conduction mode (ccm) occurs when the output current is high and the inductor current is always above zero amps (see figure 2). when v fb is below v ref , the hs-fet is turned on for a fixed interval, which is determined by the one-shot on timer. when the hs-fet is turned off, the ls-fet is turned on until the next period. figure 2: ccm operation in ccm operation, the switching frequency is fairly constant (pwm mode). light-load operation when the load decreases, the inductor current decreases as well. once the inductor current reaches zero, the MP8719 transitions from ccm to discontinuous conduction mode (dcm). dcm operation is shown in figure 3. when v fb is below v ref , the hs-fet is turned on for a fixed interval, which is determined by the one-shot on timer. when the hs-fet is turned off, the ls-fet is turned on until the inductor current reaches zero. in dcm operation, the v fb does not reach v ref when the inductor current is approaching zero. the ls-fet driver turns into tri-state (hi-z) when the inductor current reaches zero. a current modulator takes over the control of the ls-fet and limits the inductor current to less than -1ma. therefore, the output capacitors discharge slowly to gnd through the ls-fet. as a result, efficiency during light-load condition is improved greatly. the hs-fet does not turn on as frequently during light-load condition as it does during heavy-load condition (skip mode). at a light-load or no-load condition, the output drops very slowly, and the MP8719 reduces the switching frequency naturally, achieving high efficiency at light load. figure 3: dcm operation
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo MP8719 rev1.01 www.monolithicpower.com 12 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. as the output current increases from light-load condition, the current modulation regulation time period becomes shorter. the hs-fet is turned on more frequently, making the switching frequency increase. the output current reaches the critical level when the current modulator time is zero. the critical level of the output current is determined with equation (1): in s out out in critical _ out v f l v ) v v ( i ? ? ? ? ? ? 2 (1) the MP8719 enters pwm mode once the output current exceeds the critical level. afterward, the switching frequency remains fairly constant over the output current range. jitter and fb ramp jitter occurs in both pwm and skip mode when noise in the v fb ripple propagates a delay to the hs-fet driver (see figure 4 and figure 5). jitter affects system stability, with noise immunity proportional to the steepness of v fb ?s downward slope, so the jitter in dcm is usually larger than it is in ccm. however, v fb ripple does not affect noise immunity directly. v re f v fb hs driver v noise j itter v s l o pe1 figure 4: jitter in pwm mode v fb hs driver jitter v ref v slope2 v noise figure 5: jitter in skip mode operating without external ramp compensation the traditional cot control scheme is intrinsically unstable if the output capacitor?s esr is not large enough to act as an effective current-sense resistor. usually, ceramic capacitors cannot be used directly as output capacitors. the MP8719 has built-in internal ramp compensation to ensure that the system is stable, even without the help of the output capacitor?s esr. use the pure ceramic capacitor solution, which reduces the output ripple, total bom cost, and board area significantly. figure 6 shows a typical output circuit in pwm mode without an external ramp circuit. refer to the application information section on page 16 for design steps without external compensation. figure 6: simplified output circuit when using a large capacitor (e.g.: oscon) on the output, add a >10f ceramic capacitor in parallel to minimize the effect of esl. operating with external ramp compensation usually, the MP8719 is able to support ceramic output capacitors without an external ramp. however in some cases, the internal ramp may not be enough to stabilize the system, or there is too much jitter, which requires external ramp compensation. refer to the application information section on page 16 for design steps with external ramp compensation. vtt and vttref the MP8719 integrates high performance, low dropout linear regulators (vtt and vttref) to provide complete ddr3/ddr3l power solutions. the vttref has a 10ma sink/source current capability and always tracks half of vddq with 1% accuracy using an on-
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo preliminary specifications subject to change MP8719 rev. 1.01 www.monolithicpower.com 13 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. chip divider. a minimum 0.22 f ceramic capacitor must be connected close to the vttref terminal for stable operation. vtt responds quickly to track vttref with 30mv in all conditions. the current capability of the vtt regulator is up to 1a for both sink and source modes. a minimum 22 f ceramic capacitor must be connected close to the vtt terminal. vtts should be connected to the positive node of the remote vtt output capacitor as a separate trace from the high- current line to vtt. configuring the en control the MP8719 has two enable pins to turn the internal regulators on or off (en1, en2). when en1 and en2 are high, vddq, vttref and vtt are turned on. when en1 is low and en2 is high, vddq and vttref remain on while vtt is turned off and left at a high-impedance state (hi-z). the vtt output floats and does not sink or source current in this state. when en1 and en2 are low, all of the regulators remain off and discharge to gnd through a soft shutdown(see table 1). table 1: en1/en2 control en1 en2 v ddq v ttref v tt high high on on on low high on on off (hi-z) low low off off off high low off off off ultrasonic mode (usm) ultrasonic mode (usm) is designed to keep the switching frequency above an audible frequency area during light-load or no-load conditions. once the part detects that both the hs-fet and the ls-fet are off for about 32s), pwm is forced to initiate t on , so the switching frequency is out of the audible range. to prevent v out from rising too high, the MP8719 reduces t on to control v out . if the MP8719?s fb is still too high after reducing t on to the minimum value, the output discharge function is activated and keeps v out within a reasonable range. usm is selected by mode. mode selection the MP8719 implements mode for multiple applications for usm and switching frequency selection. usm and the switching frequency can be selected by a different resistor on the 3v3 logic mode pin. there are four modes that can be selected for normal application with external resistors (see table 2). it is recommended to use a 1% accuracy resistor. table 2: mode selection state usm fs resistor to gnd m1 no 700khz 0 ? m2 yes 700khz 90k ? m3 no 500khz 150k ? m4 yes 500khz >230k ? or float vddq power good (pg) the MP8719 uses a power good (pg) output to indicate whether the output voltage of the vddq regulator is ready. pg is the open drain of a mosfet. it should be connected to v cc or another voltage source through a resistor (e.g.: 100k ? ). after the input voltage is applied, the mosfet is turned on, so pg is pulled to gnd before ss is ready. after v fb reaches 95% of v ref , pg is pulled high (after a delay time within 10s). when v fb drops to 90% of v ref , pg is pulled low. soft start (ss) the MP8719 employs a soft-start (ss) mechanism to ensure a smooth output during power-up. when en becomes high, the internal reference voltage ramps up gradually, and the output voltage ramps up smoothly as well. once the reference voltage reaches the target value, the soft start finishes, and the MP8719 enters steady-state operation (see figure 7). figure 7: start-up power sequence
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo MP8719 rev1.01 www.monolithicpower.com 14 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. if the output is pre-biased to a certain voltage during start-up, the ic disables the switching of both the high-side and low-side switches until the voltage on the internal reference exceeds the sensed output voltage at the fb node. soft shutdown the MP8719 employs a soft shutdown mechanism for ddr to ensure that vttref and vtt follow exactly half of the vddq. when en2 is low, the internal reference then ramps down gradually, so the output voltage falls linearly (see figure 8). figure 8: soft shutdown sequence vddq over-current limit (ocl) the MP8719 has cycle-by-cycle over-current limiting control. the current-limit circuit employs a valley current-sensing algorithm. the MP8719 uses the r ds(on) of the ls-fet as a current- sensing element. if the magnitude of the current-sense signal is above the current-limit threshold, the pwm is not allowed to initiate a new cycle, even if fb is lower than ref (see figure 9). figure 9: valley current-limit control since the comparison is done during the ls- fet on state, the oc trip level sets the valley level of the inductor current. the maximum load current at the over-current threshold (i oc ) can be calculated using equation (2): ? ?? inductor oc i ii_limit 2 (2) the over-current limit (ocl) limits the inductor current and does not latch off. in an over- current condition, the current to the load exceeds the current to the output capacitor, so the output voltage tends to fall off. eventually, the currents ends up crossing the under-voltage protection (uvp) threshold and latches off. fault latching can be reset by en going low or cycling the power of vin. vtt/vttref over-current protection (ocp) the vtt ldo has an internal, non-latched, fixed current limit of 1.5a for both sink and source operation. once the current limit is reached, the gate of the sink/source mosfet is adjusted to limit the current. vttref also has an internal non-latch 15ma current limit. vddq over/under-voltage protection (ovp, uvp) the MP8719 monitors a resistor divided feedback voltage to detect over and under voltage. when the feedback voltage rises higher than 130% of the target voltage, the ovp comparator output goes high, the circuit latches as the hs-fet turns off, and the ls- fet turns on, acting as a -2a current source. to protect the MP8719 from damage, there is an absolute 3.6v ovp on v out . once v out reaches this value, it latches off as well. the ls-fet behaves the same as it does at 130% ovp. when the feedback voltage drops below 75% of v ref , but remains higher than 50% of v ref , the uvp-1 comparator output goes high, and the MP8719 latches if v fb remains in this range for about 30s (latching the hs-fet off and the ls-fet on). the ls-fet remains on until the inductor current reaches zero. during this period, the valley current limit helps control the inductor current.
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo MP8719 rev1.01 www.monolithicpower.com 15 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. when the feedback voltage drops below 50% of v ref , the uvp-2 comparator output goes high, and the MP8719 latches off directly after the comparator and logic delay (latching the hs- fet off and the ls-fet on). the ls-fet remains on until the inductor current reaches zero. fault latching can be reset by driving en low or cycling the power of vin. under-voltage lockout (uvlo) protection the MP8719 has two under-voltage lockout (uvlo) protections: a 3v vcc uvlo and a 4.2v vin uvlo. the MP8719 starts up only when both vcc and vin exceed their respective uvlo thresholds. the MP8719 shuts down when either vcc is lower than the uvlo falling threshold voltage (typically 2.8v) or vin is lower than the 3.9v vin falling threshold. both uvlo protections are non-latch off. if an application requires a higher under-voltage lockout (uvlo), use en2 to adjust the input voltage uvlo by using two external resistors (see figure 10). figure 10: adjustable uvlo over-temperature warning (otw) an over-temperature warning (otw) status pin is added on the MP8719 to act as a pre-over- temperature indicator. when the ic detects that it is close to its over-temperature threshold, otw pulls low and remains low for at least 10ms. otw pulls high again when the device temperature has cooled below the temperature hysteresis. otw does not trigger any protection. thermal shutdown thermal shutdown is employed in the MP8719. the junction temperature of the ic is monitored internally. if the junction temperature exceeds the threshold value (typically 145c), the converter shuts off. this is a non-latch protection. there is a hysteresis of about 25c. once the junction temperature drops to about 120c, soft start is initiated. output discharge the MP8719 discharges all the outputs including vddq, vttref, and vtt when the controller is turned off by a protection function (uvp, ocp, ovp, uvlo, or thermal shutdown). the discharge resistor on vddq is 3 ? , typically. note that the output discharge is not active during soft shutdown.
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo preliminary specifications subject to change MP8719 rev. 1.01 www.monolithicpower.com 16 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. application information setting the output voltage with no external ramp the MP8719 does not need ramp compensation for applications where poscap or ceramic capacitors are set as output capacitors (when vin is over 6v), so external compensation is not needed. the output voltage is then set by feedback resistors r1 and r2 (see figure 11). r1 r2 cap sw fb vo l c4 figure 11: simplified circuit without external ramp first, choose a value for r2. r2 should be chosen reasonably. a small value for r2 leads to considerable quiescent current loss, but an r2 value that is too large makes fb noise- sensitive. it is recommended to choose a value within 5 - 50k ? for r2. use a comparatively larger value for r2 when v out is low; use a smaller value for r2 when v out is high. considering the output ripple, determine r1 with equation (3): 2 1 r v v v r ref ref out ? ? ? (3) c4 acts as a feed-forward capacitor to improve the transient and can be set in the range of 0 - 1000pf. a larger value for c4 leads to better transient, but it is more noise sensitive. reserve room for a noise filter resistor (r9) (see figure 12). setting the output voltage with external compensation if the system is not stable enough or there is too much jitter when a ceramic capacitor is used on the output (i.e.: with a ceramic c out and vin is 5v or lower), an external voltage ramp should be added to fb through resistor r4 and capacitor c4. since there is already an internal ramp added in the system, a 1m ? (r4) 220pf (c4) ramp should suffice. figure 12: simplified circuit with external ramp besides the r1 and r2 divider, the output voltage is influenced by r4 (see figure 12). r2 should be chosen reasonably. a small value for r2 leads to considerable quiescent current loss, but a value for r2 that is too large makes fb noise sensitive. it is recommended to choose a value within 5 - 50k ? for r2. use a comparatively larger value for r2 when v out is low; use a smaller value for r2 when v out is high. the value of r1 then is determined with equation (4): 2 1 4 2 1 r r r v v v r ref out ref ? ? ? ? (4) to get a pole for better noise immunity, set r9 with equation (5): 9 4sw 1 r 2c2f ? ?? ? (5) set r9 in the range of 100 ? to 1k ? to reduce its influence on the ramp. selecting the input capacitor the input current to the step-down converter is discontinuous and therefore requires a capacitor to supply ac current to the step-down converter while maintaining the dc input voltage. for the best performance, use ceramic capacitors placed as close to vin as possible. capacitors with x5r and x7r ceramic dielectrics are recommended because they are fairly stable with temperature fluctuations. the capacitors must have a ripple current rating greater than the maximum input ripple current of the converter. the input ripple current can be estimated with equation (6): out out cin out in in vv ii (1 ) vv ?? ?? (6)
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo MP8719 rev1.01 www.monolithicpower.com 17 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. the worst-case condition occurs at vin = 2v out , shown in equation (7): out cin i i 2 ? (7) for simplification, choose an input capacitor with an rms current rating greater than half of the maximum load current. the input capacitance value determines the input voltage ripple of the converter. if there is an input voltage ripple requirement in the system, choose an input capacitor that meets the specification. the input voltage ripple can be estimated with equation (8): out out out in sw in in in iv v v(1) fc v v ?? ? ?? ? (8) the worst-case condition occurs at vin = 2v out , shown in equation (9): out in sw in i 1 v 4f c ??? ? (9) selecting the output capacitor the output capacitor is required to maintain the dc output voltage. ceramic or poscap capacitors are recommended. the output voltage ripple can be estimated using equation (10): out out out esr sw in sw out vv 1 v(1)(r ) fl v 8fc ?? ?? ? ? ??? (10) when using ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance, which mainly causes the output voltage ripple. for simplification, the output voltage ripple can be estimated with equation (11): out out out 2 sw out in vv v(1) 8f lc v ?? ?? ??? (11) the output voltage ripple caused by esr is very small. therefore, an external ramp is needed to stabilize the system. the external ramp can be generated through resistor r4 and capacitor c4. when using poscap capacitors, the esr dominates the impedance at the switching frequency. the ramp voltage generated from the esr dominates the output ripple. the output ripple can be approximated with equation (12): out out out esr sw in vv v(1)r fl v ?? ?? ? ? (12) the maximum output capacitor limitation should be considered in the design application. the MP8719 has a soft-start time period of around 1.6ms. if the output capacitor value is too high, the output voltage cannot reach the design value during the soft-start time, causing it to fail to regulate. the maximum output capacitor value (c o_max ) can be limited approximately with equation (13): o_max lim_avg out ss out c(i i)t/v ? ?? (13) where i lim_avg is the average start-up current during the soft-start period (which can be equivalent to the current limit), and t ss is the soft-start time. selecting the inductor an inductor is necessary for supplying constant current to the output load while being driven by the switched input voltage. a larger-value inductor results in less ripple current, resulting in lower output ripple voltage, but also has a larger physical footprint, a higher series resistance, and a lower saturation current. a good rule for determining the inductance value is to design the peak-to-peak ripple current in the inductor to be in the range of 30% to 50% of the maximum output current, and the peak inductor current below the maximum switch current limit. the inductance value can be calculated with equation (14): out out sw l in vv l(1) fi v ??? ?? (14) where ? i l is the peak-to-peak inductor ripple current. the inductor should not saturate under the maximum inductor peak current (including a short-current), so i sat is recommended to be >13a.
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo MP8719 rev1.01 www.monolithicpower.com 18 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. pcb layout guidelines efficient pcb layout is critical for stable operation of the ic. a 4-layer layout is strongly recommended to achieve better thermal performance. for best results, refer to figure 13 and follow the guidelines below. for more information, refer to the application note an087 ?pcb layout design guidelines for nb68x families.? 1. keep the vddq trace width greater than 100mil to avoid a voltage drop at the input of the vttldo. 2. place the high-current paths (gnd, vin, and sw) very close to the device with short, direct, and wide traces. a thick pgnd trace under the ic should be top priority. 3. place the input capacitors as close to vin and gnd as possible on the same layer as the ic. 4. place the decoupling capacitor as close to vcc and gnd as possible. 5. keep the switching node (sw) short and away from the feedback network. 6. place the external feedback resistors next to fb. 7. ensure that there is no via on the fb trace. 8. keep the bst voltage path (bst, c3, and sw) as short as possible. 9. keep the vin and gnd pads connected with a large copper plane to achieve better thermal performance. 10. add several vias with 10mil drill/18mil copper width close to the vin and gnd pads to help thermal dissipation. sw vout pgnd to agnd agnd mode fb pgnd v i n otw vtt sw vtts en2 vttref bst 1 2 9 10 en1 3v3 vddq pg 15 16 13 14 12 11 7 8 5 6 4 3 agnd?pgnd kelvin connection >100mil to vout otw vout vcc pg l 7mm*6.6mm 0805 0603 0402 vin figure 13: recommended pcb layout
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo MP8719 rev1.01 www.monolithicpower.com 19 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. design example for applications that need currents over 10a, it is recommended to apply a 500khz f sw part for better thermal performance and efficiency (see table 3). otherwise, a 700khz f sw operation makes the system more compact with faster transient (see table 4). there is a resistor from an external 3.3v supply to 3v3 acting as a ripple noise filter of the 3.3v power supply. it is recommended to have a resistor value from 0 - 5.1 ? depending on the noise level. a size 0402 resistor is sufficient if the 3.3v voltage rises up with ss > 100s. otherwise, a larger resistor (e.g.: 0603/0805) is needed. for applications where vin is 5v or lower, it is recommended to apply the sch shown in figure 14 with a proper external ramp. the MP8719 also supports non ddr applications with very compact external components (see figure 15). some design examples are provided below when ceramic capacitors are applied. table 3: design example for 500khz f sw v out (v) cout (f) l ( h) r mode ( ? ) c4 (pf) r1 (k ? ) r2 (k ? ) 1.0 22 x4 1.0 150k 220 13.3 20 1.2 22 x4 1.0 150k 220 20 20 1.35 22 x4 1.0 150k 220 28 22.1 1.5 22 x4 1.2 150k 220 30.1 20 1.8 22 x4 1.5 150k 220 40.2 20 table 4: design example for 700khz f sw v out (v) cout (f) l ( h) r mode ( ? ) c4 (pf) r1 (k ? ) r2 (k ? ) 1 22 x3 0.68 0 220 13.3 20 1.2 22 x3 0.68 0 220 20 20 1.35 22 x3 0.68 0 220 28 22.1 1.5 22 x3 0.68 0 220 30.1 20 1.8 22 x3 0.68 0 220 40.2 20 additional design examples with higher v out the MP8719 supports designs that need v out to be in the range of 3.3v to 5.5v. figure 17 shows an sch with a 5v v out with proper external settings. please pay attention to the red components, and please note that usm is not allowed for this application.
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo MP8719 rev. 1.01 www.monolithicpower.com 20 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical application circuits ddr application for vin >6v en 1 fb bst vin pg sw en 2 pgnd 3v3 mode vddq vtt vttsen agnd vttref otw ddr_vtt_control en 2 figure 14: typical ddr applicati on circuit, vin = 6v - 24v, v out = 1.35v, i out = 10a, with vtt fs = 700khz ddr application cover 5v vin application figure 15: typical ddr application circuit, vin = 4.5v - 24v, v out = 1.35v, i out = 10a, with vtt fs = 700khz
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo MP8719 rev. 1.01 www.monolithicpower.com 21 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical application circuits (continued) non ddr application figure 16: normal single buck applicat ion circuit, vin = 4.5v - 24v, v out = 1v, i out = 10a, without vtt fs = 700khz special application with 3.3v < vout < 5.5v figure 17: special application circuit, vin = 7v - 22v, v out = 5v, i out = 10a, fs = 700khz note 1: ultrasonic mode is not effective if applied in this sch. note 2: the maximum load is 10a in this application. fs is set with a 500khz mode but is actually 700khz. note 3: it is recommended to avoid vddq voltages over 3.3v by using the external resistors setting.
MP8719 ? 26v, 12a, high-current, sync buck converter with 1a ldo notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP8719 rev. 1.01 www.monolithicpower.com 22 8/3/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. package information qfn-16 (3mmx3mm)

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